Addressing Floorplanning Impact on Performance - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-05-30
Version
2024.1 English

Before you begin floorplanning, ensure that key resources are available on your Versal device. These resources can include the AI Engine array interface (or shim tile), block RAM, UltraRAM, DSP, NoC, and DDRMC.

The following figure shows the XCVC1902 in the Vivado IDE Device window with key resources highlighted. The figure also shows how the fabric memory resources are distributed across the device, such as block RAM or UltraRAM. Aligning the floorplan based on the connectivity of the input/output stream of logic is crucial to achieving better system performance. Following are some examples for input and output stream of logic:

  • AI Engine-PL-NoC-DDRMC
  • AI Engine-PL
  • PS-NoC-DDRMC
Figure 1. Versal Device Key Resources

The following figure shows an example of floorplanning the AI Engine and PL. In this design, there is AI Engine-PL dataflow, and the PL does not use UltraRAM resources. If only block RAM resources are used as part of the dataflow interacting with the AI Engine array interface, the AI Engine streams can be floorplanned in a region where the PL is mapped to a portion of the device without UltraRAM columns.

Figure 2. AI Engine and PL Floorplanning

The following figure addresses designs with GMIOs in the AI Engine that read/write to the DDRMC through the NoC. There are specific columns in the AI Engine that support GMIOs. The following figure shows an XCVC1902 in the Device window with 16 GMIO-capable columns. Following are considerations for accessing GMIO-capable columns:

  • Supply proper QoS requirements, allowing the NoC compiler to maximize bandwidth allocated to the paths.
  • Allow the aiecompiler to select GMIO columns and the NoC compiler to select the appropriate DDRMC location based on QoS settings.
  • If needed, constrain GMIOs to appropriate columns above the vertical NoCs (VNoCs), and also constrain DDRMC below the VNoCs to minimize latency through the NoC.
Figure 3. GMIO-Capable Columns