Reviewing Clock Relationships - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-06-19
Version
2024.1 English

You can view the relationship between clocks using the report_clock_interaction Tcl command. The report shows a matrix of source clocks and destination clocks. The color in each cell indicates the type of interaction between clocks, including any existing constraints between them. The following figure shows a sample clock interaction report.

Figure 1. Sample Clock Interaction Report

The following table explains the meaning of each color in this report.

Table 1. report_clock_interaction Colors
Color Label Meaning What Next
Black No path No interaction among these clock domains. Primarily for information unless you expected these clock domains to be interacting.
Green Timed There is interaction among these clock domains, and the paths are getting timed. Primarily for information unless you do not expect any interaction among the clock domains.
Cyan Partial False Path Some of the paths for the interacting domains are not being timed due to user exceptions. Ensure that the timing exceptions are really desired.
Red Timed (unsafe) There is interaction among these clock domains, and the paths are being timed. However, the clocks appear to be independent (and hence, asynchronous). Check whether these clocks are supposed to be declared as asynchronous, or whether they are supposed to be sharing a common primary source.
Orange Partial False Path (unsafe) There is interaction among these clock domains. The clocks appear to be independent (and hence, asynchronous). However, only some of the paths are not timed due to exceptions. Check why some paths are not covered by timing exceptions.
Blue User Ignored Paths There is interaction among these clock domains, and the paths are not being timed due to clock groups or false path timing exceptions. Confirm that these clocks are supposed to be asynchronous. Also, check that the corresponding HDL code is written correctly to ensure proper synchronization and reliable data transfer across clock domains.
Light blue Max Delay Datapath Only There is interaction among these clock domains, and the paths are getting timed through: set_max_delay -datapath_only. Confirm that the clocks are asynchronous and that the specified delay is correct.

Before the creation of any false paths or clock group constraints, the only colors that appear in the matrix are black, red, and green. Because all clocks are timed by default, the process of decoupling asynchronous clocks takes on a high degree of significance. Failure to decouple asynchronous clocks often results in a highly over-constrained design.