Revision History - 2024.2 English - UG1388

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-12-18
Version
2024.2 English

The following table shows the revision history for this document.

Section Revision Summary
12/18/2024 Version 2024.2
Selecting the Optimal Vertical Tree Clock Configuration Added new section.
XPHY Interface Timing Added new section.
Predefined Strategies Added recommended strategies.
Custom Strategies Added recommended options.
06/19/2024 Version 2024.1
Review the Logic Level and Routes Distribution Tables Added information on Route Distribution table.
Improving Performance Through the CPM and PL PCIE Added pointers to more information.