For paths that have large hold violations (> 0.4 ns), it is
advantageous to reduce the hold violations prior to routing the design, making it easier
for the router to fix the remaining smaller hold violations using route detours.
Reducing hold violations prior to routing can be beneficial if hold fixing has been
identified as a source of routing congestion. The phys_opt_design
hold fixing options each use different resources and have
specific targets. It is important to use the proper option depending upon the device
utilization and desired impact. Prior to running phys_opt_design
for hold fixing, it is important to validate that the
design has properly constrained clocktrees for minimal skew.
You can also insert LUT1 delays onto datapaths to reduce hold violations.
To insert LUT1 delays, use one of the following options during the phys_opt_design
implementation step:
-
-hold_fix
- Performs LUT1 insertion and only considers paths that are the largest WHS violators with sufficient positive setup slack.
-
-aggressive_hold_fix
- Performs LUT1 insertion in a more aggressive manner than the standard
-hold_fix
option. The-aggressive_hold_fix
optimization considers many hold violating paths for LUT1 insertion and can be used to significantly reduce design THS at the expense of LUT utilization.
The following figure shows a LUT1 delay inserted after a flip-flop driving an ILKN block. Before the optimization, the path from the flip-flop to the ILKN is the WHS path in the design with -0.277 ns hold slack. After the insertion of the LUT1 delay (highlighted in blue), the hold slack is positive and the setup slack remains positive.