Analyzing System Performance in Simulation - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-06-19
Version
2024.1 English

When analyzing system performance in simulation, the critical data paths are between the AI Engines, PL, NoC (DDR), and high-speed transceivers. Before the system is integrated, you must ensure that each block meets its performance estimates.

Note: For traditional designs without a platform for use in the Vitis tools, system performance analysis is based on RTL simulation and hardware debug features, such as ChipScopeā„¢ debug IP cores and dedicated hard block debug features.