report_qor_suggestions Tcl command.High fanout nets in slower clock domains can be moved onto the
global routing by inserting a clock buffer between the driver and the loads.
This optimization is automatically performed in opt_design for nets with a fanout greater than 25000 only
when a limited number of clock buffers are already used and the clock period
of the logic driven by the net is above the limit specific to the targeted
device and speed grade. To support
high fanout nets on global routing in Versal devices, BUFG_FABRIC cells can be placed
on BUFG_FABRIC sites that exist throughout the device in NoC
columns.
You can force synth_design and
opt_design to insert a clock buffer
when setting the CLOCK_BUFFER_TYPE attribute on a net in the RTL file or in
the constraint file (XDC). For example:
set_property CLOCK_BUFFER_TYPE BUFG_FABRIC [get_nets netName]Using global clocking ensures optimal routing at the cost of
higher net delay. For optimal routing delays, clock buffers must drive
sequential loads directly, without intermediate combinatorial logic. In most
cases, opt_design reconnects non-sequential
loads in parallel to the clock buffer. If needed, you can prevent this
optimization by applying a DONT_TOUCH on the clock buffer output net. Also,
if the high fanout net is a control signal, you must identify why some loads
are not dedicated clock enable or set/reset pins.
The placer also automatically routes high fanout nets (fanout
> 10000) on any global routing tracks available after clock routing is
performed. This optimization occurs towards the end of the placer flow and
is only performed if timing does not degrade. You can disable this feature
using the -no_bufg_opt option.