ILA Core and Timing Considerations - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)
Document ID
UG1388
Release Date
2024-06-19
Version
2024.1 English

The configuration of the ILA core has an impact in meeting the overall design timing goals. Follow the recommendations below to minimize the impact on timing:

  • Choose probe width judiciously. The bigger the probe width the greater the impact on both resource utilization and timing.
  • Choose ILA core data depth judiciously. The bigger the data depth the greater the impact on both block RAM resource utilization and timing.
  • Ensure that the clock chosen for the AXIS-ILA clk port is a free-running clock. Failure to do so could result in an inability to communicate with the debug core when the design is loaded onto the device.
  • Ensure that the clock connected to the AXI4 debug hub is a free running clock and is synchronous to the AXI master that is connected to the S_AXI port. Failure to do so could result in an inability to communicate with the debug core when the design is loaded onto the device.

  • Make sure the clock input to the ILA core is synchronous to the signals being probed. Failure to do so results in timing issues and communication failures with the debug core when the design is programmed into the device.

  • Make sure that the design meets timing before running it on hardware. Failure to do so results in unreliable probed waveforms.

The following table shows the impact of using specific ILA features on design timing and resources.

Note: This table is based on a design with one ILA and does not represent all designs.
Table 1. Impact of ILA Features on Design Timing and Resources
ILA Feature When to Use Timing Area
Capture Control/ Storage Qualification

To capture relevant data

To make efficient use of data capture storage (block RAM)

 Medium to High Impact
  • No additional block RAMs
  • Slight increase in LUT/FF count
Advanced Trigger

When BASIC trigger conditions are insufficient

To use complex triggering to focus in on problem area

 High Impact
  • No additional block RAMs
  • Moderate increase in LUT/FF count

Number of Comparators per Probe Port

Note: Maximum is 4.

To use probe in multiple conditionals:

  • 1-2 for Basic
  • 1-4 for Advanced
  • +1 for Capture Control
 Medium to High Impact
  • No additional block RAMs
  • Slight to moderate increase in LUT/FF count
Data Depth To capture more data samples High Impact
  • Additional block RAMs per ILA core
  • Slight increase in LUT/FF count
ILA Probe Port Width To debug a large bus versus a scalar Medium Impact
  • Additional block RAMs per ILA core
  • Slight increase in LUT/FF count
Number of Probes Ports To probe many nets Low Impact
  • Additional block RAMs per ILA core
  • Slight increase in LUT/FF count
Tip: In the early stages of the design, there are usually many spare resources in the device that can be used for debugging.