Debugging power typically involves a system-level simulation tool and hardware measurement. For information on debugging power issues, see the following resources:
- Power analysis and power optimization or reduction
For tips and techniques on power reduction when the power budget is exceeded, see this link in the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907).
- Power distribution systems (PDS) and power distribution networks
(PDN)
For information on ensuring that the power ripple is within the specifications, see this link in the Versal Adaptive SoC PCB Design User Guide (UG863), and see Simulating FPGA Power Integrity Using S-Parameter Models (WP411).
- Power-on and power sequence issues
If you have power-on or power sequence issues, see the Simplified Power Sequencing Application Note (XAPP1375) for information on different sequencing behaviors and how to implement the correct power sequence.
- Correlation issues between power estimation, thermal simulation, and
hardware measurement
- Hardware measurement
For information on achieving a more accurate power estimation, see this link in the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907). For a measurement debug guide and for information on getting a more accurate power and Junction temperature, see this link in the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907).
- Thermal design solution and debug issues
For information on thermal specifications and management, see the Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013). For best practices with heatsink solutions, see Designing Heatsinks and Thermal Solutions for Xilinx Devices (XAPP1377).
- Hardware measurement
- Power management issues
For information, see the Power Management - Getting Started Wiki and the Power Efficiency Web page.