Debugging the DDR Memory Controllers - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-06-19
Version
2024.1 English

The integrated DDR memory controllers support both DDR4 and LPDDR4/4X memory interfaces. The DDR memory controllers have four programmable NoC interface ports and are designed to handle multiple streams of traffic. Five quality of service (QoS) classes are available to ensure appropriate prioritization of commands. The controller accepts burst transactions and implements command reordering to maximize efficiency of the memory interface. Optional external interface reliability features include ECC error detection/correction and command address parity. For more information on the DDR memory controller features, functionality, and interaction with the NoC, see the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).