Functional Validation - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-05-30
Version
2024.1 English

Functional validation involves checking the functional integrity of the graph in the AI Engine. This can be achieved using the validation methods described earlier, such as using ATGs/AXI DMA/MCDMAs/S2MM-MM2S HLS based kernels to directly transmit test data from DDR memory to AI Engines. This is the simplest method to test the functionality of graphs within the AI Engines.

To program AI Engines, start the graphs, and orchestrate data flow, the design must be Vitis compliant. For more information, see the Versal Adaptive SoC Design Guide (UG1273). You can use the Vitis platforms, provided with the Vitis installation tools, and build the validation design based. Additionally, enabling AI Engines does not require a software host application, but a baremetal-based host application is required to leverage all the features of AI Engine tools as described in the AI Engine Tools and Flows User Guide (UG1076).