Constraining Clock Domain Crossings - 2023.2 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2023-11-15
Version
2023.2 English

Upon verification of the clocking constraints, you must identify asynchronous and over-constrained clock domain crossing paths.

Note: This section does not explain how to properly cross clock region boundaries. Instead, it explains how to identify which crossings exist and how to constrain them.