Creating the Device Image - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-05-30
Version
2024.1 English

After synthesis and implementation are complete, a device image must be created for the design to run on the target device. AMD Versal™ device architectures use a device image in the programmable device image (.pdi) file format. You can create the device image using the write_device_image Tcl command or by clicking Generate Device Image in the AMD Vivado™ IDE. Prior to device image creation, a DRC is run and any Critical Warnings generated during early design stages are elevated to Errors, preventing device image creation. For more information on creating a device image, see the Vivado Design Suite User Guide: Programming and Debugging (UG908).

For DFX designs, the write_device_image command supports a -cell switch, which accepts the reconfigurable module name as an argument. If -cell is not specified, write_device_image generates both full and partial PDI files. If partial PDI files are not required, you can use the -no_partial_pdifile switch to generate only the full PDI file. For Versal devices, file compression and per-frame cyclic redundancy checks (CRCs) are enabled by default for partial PDI files. For details regarding different partial PDI delivery mechanism to hardware, see the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).

Important: In addition to resolving all DRC errors prior to creating the design PDI file, you must ensure that timing requirements are met and important methodology checks are addressed. The report_timing_summary command provides timing slack information, and the report_methodology command flags design or constraints issues that can lead to hardware instability or failure.
Note: For designs that use advanced device management features enabled via the CIPS PMC IP, you must run the Bootgen tool to complete the PDI with the PMC firmware, similar to the embedded software development flow. For more information, see this link in the Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400).