SRL_STAGES_TO_REG_OUTPUT - 2022.1 English

Vivado Design Suite Properties Reference Guide

Document ID
UG912
Release Date
2022-06-08
Version
2022.1 English
SRL_STAGES_TO_REG_OUTPUT

SRL_STAGES_TO_REG_OUTPUT

A register stage can be pulled out from SLR output or pushed into SRL output using the SRL_STAGES_TO_REG_OUTPUT property.

This provides control on pipeline register structures to address under and over-pipeline at the output side of SRL primitives.

Architecture Support

All architectures.

Applicable Objects

• Cells (get_cells) as leaf level SRL instances.

Value

1: The Vivado logic optimization will pull out a register from the specified SRL primitive(s) output.

-1: The Vivado logic optimization will push a register into a specified SRL primitive(s) output.

Syntax

Verilog and VHDL Syntax

Not applicable

XDC Syntax

set_property SRL_STAGES_TO_REG_OUTPUT  <1 | -1> <objects>

The objects should be SRLs, and the registers to be absorbed into the same SRL should share the same control set with no reset.

XDC Example:

set_property SRL_STAGES_TO_REG_OUTPUT 1 [get_cells {cell1 cell2}]

Affected Steps

Opt Design

See Also

REG_TO_SRL

SRL_TO_REG

SRL_STAGES_TO_REG_INPUT