REG_TO_SRL - 2022.1 English

Vivado Design Suite Properties Reference Guide

Document ID
UG912
Release Date
2022-06-08
Version
2022.1 English
REG_TO_SRL

REG_TO_SRL

A chain of register primitives can be converted to a logically equivalent SRL primitive using the REG_TO_SRL property with a value of true. This transform is typically used to reduce the number of pipeline register stages used by signals to traverse long distances within a device. Having too many register stages can create congestion or other placement problems.

Architecture Support

All architectures.

Applicable Objects

• Cells (get_cells) as leaf level register instances.

Value

True (or 1): The Vivado logic optimization will convert the specified register primitives into a SRL.

False (or 0): The Vivado logic optimization will not convert the specified register primitives into a SRL.

Syntax

Verilog and VHDL Syntax

Not applicable

XDC Syntax

set_property REG_TO_SRL <True | False> <objects>

The property is false by default. The objects should be registers, and the registers to be absorbed into the same SRL should share the same control set with no reset.

XDC Example:

set_property REG_TO_SRL 1 [get_cells {cell1 cell2}]

Affected Steps

Opt Design

See Also

SRL_TO_REG