SLEW specifies output buffer slew rate for output buffers configured with I/O standards that support programmable output slew rates.
Architecture Support
All architectures.
Applicable Objects
•Ports (get_ports)
°Output or bidirectional ports connected
•Cells (get_cells)
°Output Buffers (all OBUF variants)
Values
•SLOW (default)
•MEDIUM: for UltraScale architecture, only available on high-performance (HP) I/Os.
•FAST
Syntax
Verilog Syntax
To set this attribute when inferring I/O buffers, place the proper Verilog attribute syntax before the top-level output port declaration.
(* DRIVE = "{SLOW|FAST}" *)
Verilog Syntax Example
// Sets the Slew rate to be FAST
(* SLEW = "FAST" *) output FAST_DATA,
VHDL Syntax
To set this attribute when inferring I/O buffers, place the proper VHDL attribute syntax before the top-level output port declaration.
Declare the VHDL attribute as follows:
attribute SLEW : string;
Specify the VHDL attribute as follows:
attribute SLEW of port_name : signal is value;
Where
•port_name is a top-level output port.
VHDL Syntax Example
FAST_DATA : out std_logic;
attribute SLEW : string;
-- Sets the Slew rate to be FAST
attribute SLEW of STATUS : signal is “FAST”;
XDC Syntax
set_property SLEW value [get_ports port_name]
Where
•port_name is an output or bidirectional port.
XDC Syntax Example
# Sets the Slew rate to be FAST
set_property SLEW FAST [get_ports FAST_DATA]
Affected Steps
•I/O Planning
•Report Noise
•Report Power
See Also
Refer to the following design elements in the Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953) [Ref 25] or the UltraScale Architecture Libraries Guide (UG974) [Ref 26].
•OBUF
•OBUFT
•IOBUF
•IOBUF_DCIEN
•IOBUF_INTERMDISABLE