The DELAY_VALUE_XPHY property on PORT objects specifies the amount of delay to add on an input or output path for Versal XPHY Logic Interfaces. During the early phases of opt_design when the Advanced I/O Wizard IP is being regenerated, the DELAY_VALUE_XPHY value will be copied from the PORT onto the XPHY instance for the input or output path. DRCs exist in the Vivado Design Suite to ensure that the DELAY_VALUE_XPHY value aligns to the value on the XPHY instance. In the case where you want to update the amount of delay on an input or output path for an already implemented design, you can apply your new value to the PORT by using the DELAY_VALUE_XPHY property. Then, you can run the implement_xphy_cores -update_delay_value_only command to deposit the new value onto the XPHY instance.
Architecture Support
Versal architecture.
Applicable Objects
•Ports (get_ports)
Values
•For input ports without a cascade: 0 - 625 ps
•For input ports with a cascade: 0 - 1250 ps
•For output ports: 0 - 625 ps
Syntax
Verilog and VDHL Syntax
Not Applicable
XDC Syntax
set_property DELAY_VALUE_XPHY <value> [get_ports port_name]
Where
•port_name is a top-level port
XDC Syntax Example
# Open a fully implemented design
open_checkpoint top_routed.dcp
# Update the delay on the input path from PORT dataIn
set_property DELAY_VALUE_XPHY 125 [get_ports dataIn]
implement_xphy_cores -update_delay_value_only
# Write a new checkpoint and device image with the updated delay
write_checkpoint top_routed_125.dcp
write_device_image top_routed_125.pdi
Affected Steps
•Timing Analysis
•Opt Design