The AUTOPIPELINE_LIMIT property specifies the maximum limitation for the pipeline stages to be inserted by the optimization techniques.
Architecture Support
UltraScale, UltraScale+, Versal ACAP.
Applicable Objects
•Nets (get_nets)
•Cells (get_cells)
Each single net should be directly driven by a flip-flop, and the fanout load can only be 1.
Value
•<N>: This is an integer number with a limit of 24.
Syntax
VHDL Example Syntax
attribute autopipeline_limit : integer;
signal mywire: std_logic_vector(2 downto 1);
attribute autopipeline_limit of mywire: signal is "12";
Verilog Example Syntax
(* autopipeline_limit="12"*) wire mywire;
XDC Example Syntax
set_property AUTOPIPELINE_LIMIT 12 [get_nets mywire]
Affected Steps
•Place Design
•Phys Opt Design