Description
CLOCK objects provide the Vivado Design Suite a time reference for reliably transferring data from register to register. The Vivado timing engine uses the properties of the CLOCK objects to compute the setup and hold requirements of the design and report the design timing margin by means of the slack computation. You must properly define the CLOCK objects in order to get the maximum timing path coverage with the best accuracy.
A clock is defined with PERIOD and WAVEFORM properties. The period is specified in nanoseconds and defines the length of the clock cycle. It corresponds to the time over which the waveform repeats. The waveform is the list of rising edge and falling edge absolute times, in nanoseconds, within the clock period. Refer to Vivado Design Suite User Guide: Using Constraints (UG903) [Ref 19] for more information on defining clocks.
The period and waveform properties represent the ideal characteristics of a clock. When entering the FPGA and propagating through the clock tree, the clock edges are delayed and become subject to variations induced by noise and hardware behavior. These characteristics are called clock network latency and clock uncertainty. By default, the Vivado Design Suite treats all clocks as propagated clocks, or non-ideal, in order to provide an accurate slack value which includes clock tree insertion delay and uncertainty.
The Vivado tools support a variety of different types of clocks:
•Primary clocks - A primary clock is a system-level clock that enters the Vivado design through a primary input port or a gigabit transceiver pin. A primary clock is defined by the create_clock command. The design source of a primary clock defines the time zero and point of propagation used by the Vivado timing engine when computing delay values.
•Virtual clocks - A virtual clock is a CLOCK object that is not physically attached to any netlist elements in the design. A virtual clock is defined by the create_clock command, without specifying a source object to assign the clock to.
•Generated clocks - Generated clocks are driven inside the design by special cells called Clock Modifying Blocks (for example, an MMCM), or by some user logic. Generated clocks are derived from a master clock by the create_generated_clock command, and include the IS_GENERATED property. Instead of specifying the period and waveform of generated clocks, you must describe how the modifying circuitry transforms the master clock.
Clocks use dedicated device resources to propagate through the design. Refer to 7 Series FPGAs Clocking Resources User Guide (UG472) [Ref 3] or UltraScale Architecture Clocking Resources User Guide (UG572) [Ref 9] for more information on clock resources.
Related Objects
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X-Ref Target - Figure 2-13 
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CLOCK objects are related to the PORTs, NETs, CELLs, or PINs that are their source, as defined by the create_clock command. You can query the clocks associated with a netlist object using the get_clock or get_generated_clocks commands:
get_clocks -of_objects [get_ports <port_name>]
You can also query the netlist objects (NETs, PINs, PORTs) associated with clocks:
get_nets -of_objects [get_clocks]
Properties
The properties on the clock object include the following, with example values:
Property Type Read-only Visible Value
CLASS string true true clock
DIVIDE_BY int true true
DUTY_CYCLE double true true
EDGES int* true true
EDGE_SHIFT double* true true
FILE_NAME string true true
INPUT_JITTER double true true 0.000
IS_GENERATED bool true true 1
IS_INVERTED bool true true 0
IS_PROPAGATED bool true true 1
IS_RENAMED bool true true 0
IS_USER_GENERATED bool true true 0
IS_VIRTUAL bool true true 0
LINE_NUMBER int true true
MASTER_CLOCK clock true true sysClk
MULTIPLY_BY int true true 1
NAME string true true usbClk
PERIOD double true true 10.000
SOURCE pin true true clkgen/mmcm_adv_inst/CLKIN1
SOURCE_PINS string* true true clkgen/mmcm_adv_inst/CLKOUT2
SYSTEM_JITTER double true true 0.050
WAVEFORM double* true true 0.000 5.000
You can use the report_property command to report the properties of a CLOCK object. Refer to the Vivado Design Suite Tcl Command Reference Guide (UG835) [Ref 13] for more information. To report the properties for a specific clock in the design, you can use the following command in the Vivado Design Suite Tcl shell or Tcl Console:
report_property -all [get_clocks <clock_name>]
Where <clock_name> is the name of the clock to report.