By default, the Vivado Design Suite uses an out-of-context (OOC) design flow to synthesize IP cores from the Vivado IP catalog, and block designs from the Vivado IP integrator. The OOC flow reduces design cycle time, and eliminates design iterations, letting you save synthesis results in design checkpoint (DCP) files. The GENERATE_SYNTH_CHECKPOINT property determines whether the post-synthesis checkpoint will be generated as an output product for the associated IP file (XCI) or block design (BD) file. Refer to this link in the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 16], or this link in Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) [Ref 27] for more information.
The Vivado Design Suite automatically generates the synthesized design checkpoint file (DCP) needed to support the out-of-context (OOC) design flow when generating the output products for an IP or block design. OOC modules are seen as black boxes in the top-level design until the synthesized design is opened and all the OOC checkpoints are integrated.
IMPORTANT: Vivado implementation resolves black boxes by extracting the netlists from the DCP of the IP and BD.
For block design files (.bd), the SYNTH_CHECKPOINT_MODE property determines how the DCP for the block design will be synthesized. By default, the block design will be synthesized as Out-of-Context per IP, but you change the default mode by manually setting the SYNTH_CHECKPOINT_MODE property.
When generating the output products for an included IP or BD, you can decide whether to use the out-of-context flow, including the creation of a synthesis Design Checkpoint (DCP), or to let the IP be globally synthesized as part of the top-level design.
You can set the GENERATE_SYNTH_CHECKPOINT property to FALSE, or 0, to disable the OOC flow, and disable the generation of the synthesized DCP output product for specified XCI or BD files.
This property will become read-only if the IP is locked for any reason. In this case, you can run Reports > Report IP Status in the Vivado IDE, or run the report_ip_status Tcl command to see why the IP is locked. You will not be able to generate the DCP without first updating the IP to the latest version in the Vivado IP catalog. Refer to this link in the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 16] for more information.
Architecture Support
All architectures.
Applicable Objects
•IP Files (XCI) or Block Design Files (BD)
•(get_files)
Values
•TRUE: Generate the synthesis design checkpoint (DCP) as part of the output products of an IP or block design, to enable the out-of-context (OOC) design flow (default).
•FALSE: Do not generate the synthesis DCP and disable the OOC flow.
Syntax
Verilog and VHDL Syntax
Not applicable
XDC Syntax
set_property GENERATE_SYNTH_CHECKPOINT {TRUE | FALSE} [get_files <filename>]
Where
•<filename> is the filename of an IP (XCI) or of a block design (BD).
XDC Syntax Example
set_property GENERATE_SYNTH_CHECKPOINT false [get_files char_fifo.xci]
TIP: A warning will be returned by the tool if you try to assign or query the GENERATE_SYNTH_CHECKPOINT property on an object other than an XCI or BD file.
Affected Steps
•Synthesis
•Implementation
See Also
SYNTH_CHECKPOINT_MODE, page 390