The Boundary Logic Interface (BLI) constraint instructs the Vivado placer to place a flip flop cell into the BLI resources that exist at the interface between Programmable Logic and XPIO/AIE resources. BLI resources can help optimize the timing of the interface. The Vivado placer will only place the flip-flop cell into the BLI resource if connectivity, control set, and initial value criteria are met.
Architecture Support
Versal ACAP
Applicable Objects
•Flip-flop cells (get_cells) connected to applicable XPIO or AI Engine primitives.
Values
•TRUE: The flip-flop cell will be placed into the BLI resource if connectivity, control set, and initial value criteria are met.
•FALSE: The flip-flop cell will not be placed into the BLI resource (default).
•AUTO: Currently unsupported.
Syntax
Verilog and VHDL Syntax
Not applicable
XDC Syntax
set_property BLI <TRUE | FALSE> [get_cells <ff_cells>]
XDC Syntax Examples
# Use BLI Flip flop
set_property BLI TRUE [get_cells myHier/myBliFlop]
Affected Steps
•Implementation
See Also
•Versal ACAP AI Engine Architecture Manual (AM009) [Ref 33]
•Versal ACAP SelectIO Resources Architecture Manual (AM010) [Ref 34]