BEL specifies the placement of a leaf-level Cell within a SLICE/CLB, or other site which can contain multiple cells. BEL is typically used with an associated LOC property to specify the exact placement of a register or LUT.
IMPORTANT: The BEL property or constraint must be defined prior to the LOC property or constraint, or a placement error is returned.
Architecture Support
All architectures.
Applicable Objects
•Cells (get_cells)
°Register (FD, FDCE, FDPE, FDRE, FDSE)
°LUT (LUT1, LUT2, LUT3, LUT4, LUT5, LUT6, LUT6_2)
°SRL (SRL16E, SRLC32E)
°LUTRAM (RAM32X1S, RAM64X1S)
°Configuration Components (BSCAN, ICAP, etc.)
Values
•BEL = <name> BEL names can take many different forms depending on the specific logic contents of the BEL. BEL names can also hierarchically include the SITE name for the BEL. For instance, some valid BEL names are BSCAN_X0Y0/BSCAN, and SLICE_X1Y199/A5FF.
Syntax
Verilog Syntax
Place the Verilog attribute immediately before the instantiation. The Verilog attribute can also be placed before the reg declaration of an inferred register, SRL, or LUTRAM.
(* BEL = "site_name" *)
Verilog Syntax Example
// Designates placed_reg to be placed in FF site A5FF
(* BEL = "A5FF" *) reg placed_reg;VHDL Syntax
Declare the VHDL attribute as follows:
attribute BEL : string;
For an instantiated instance, specify the VHDL attribute as follows:
attribute BEL of instance_name : label is "site_name";
Where
•instance_name is the instance name of an instantiated register, LUT, SRL, or LUTRAM.
VHDL Syntax Example
-- Designates instantiated register instance placed_reg to be placed in FF site A5FF
attribute BEL of placed_reg : label is "A5FF";
For an inferred instance, specify the VHDL attribute as follows:
attribute BEL of signal_name : signal is "site_name";
Where
•signal_name is the signal name of an inferred register, LUT, SRL, or LUTRAM.
VHDL Syntax Example
-- Designates instantiated register instance placed_reg to be placed in FF site A5FF
attribute BEL of placed_reg : signal is "A5FF";
XDC Syntax
set_property BEL site_name [get_cells instance_name]
Where
•instance_name is a register, LUT, SRL, or LUTRAM, or other cell instance.
XDC Syntax Example
# Designates placed_reg to be placed in FF site A5FF
set_property BEL A5FF [get_cells placed_reg]
Affected Steps
•Design Floorplanning
•Place Design
See Also