MAX_FANOUT - 2022.1 English

Vivado Design Suite Properties Reference Guide

Document ID
UG912
Release Date
2022-06-08
Version
2022.1 English

MAX_FANOUT

MAX_FANOUT instructs Vivado synthesis on the fanout limits for registers and signals, after which the driver must be replicated. The value is specified as an integer.

MAX_FANOUT overrides the default value of the global synthesis option -fanout_limit. You can set the default limit for a design from the Synthesis page of the Tools > Settings command, or by using the -fanout_limit command line option of the synth_design command.

 

IMPORTANT:   During Vivado synthesis, the MAX_FANOUT attribute is enforced whereas the -fanout_limit constitutes only a guideline for the tool, not a strict command. When strict fanout control is required, use MAX_FANOUT. Also, unlike the -fanout_limit switch, MAX_FANOUT can impact control signals. The -fanout_limit switch does not impact control signals (such as set, reset, clock enable), use MAX_FANOUT to replicate these signals if needed.

This attribute only works on registers and combinatorial signals. To meet the specified fanout limit, Vivado synthesis replicates the register or the driver that drives the combinatorial signal. This attribute can be set in the RTL or the XDC.

MAX_FANOUT is also used during placement optimization when the placer can replicate registers driving high-fanout nets, or registers driving nets with loads that are placed far apart, or nets with a MAX_FANOUT property value that has not been satisfied. Fanout optimization occurs early in the placement flow, reducing the timing criticality of paths before starting detailed placement.

When the MAX_FANOUT value is less than the actual fanout of the constrained net the net is always evaluated for replication, but the optimization can be skipped if timing does not improve. The post-replication fanout will not necessarily match the MAX_FANOUT constraint value.

Architecture

All devices.

Applicable Elements

Registers and combinatorial signals in RTL and net objects in synthesized designs.

Values

<Integer>: Specifies maximum limit of fanout, after which the driver is replicated.

Syntax

Verilog Syntax

On Signal:

(* max_fanout = 50 *) reg sig1;

VHDL Syntax

signal sig1 : std_logic;

attribute max_fanout : integer;

attribute max_fanout of sig1: signal is 50;

XDC Syntax

set_property MAX_FANOUT <number> [get_nets -hier <net_name>]

Affected Steps

Synthesis

Place Design