DCI_CASCADE defines a master-slave relationship between a set of high-performance (HP) I/O banks. The digitally controlled impedance (DCI) reference voltage is chained from the master I/O bank to the slave I/O banks.
DCI_CASCADE specifies which adjacent banks use the DCI Cascade feature, thereby sharing reference resistors with a master bank. If several I/O banks in the same I/O bank column are using DCI, and all of those I/O banks use the same VRN/VRP resistor values, the internal VRN and VRP nodes can be cascaded so that only one pair of pins for all of the I/O banks in the entire I/O column is required to be connected to precision resistors. DCI_CASCADE identifies the master bank and all associated slave banks for this feature. Refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 2], or the UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 8] for more information.
Architecture Support
•Kintex®-7 devices.
•Kintex UltraScale devices.
•Virtex®-7 devices.
•Virtex UltraScale devices.
•Larger Zynq®-7000 SoC devices.
Applicable Objects
•I/O Bank (get_iobanks)
°High Performance (HP) bank type
Values
Valid High Performance (HP) bank numbers. See the 7 Series FPGAs Packaging and Pinout Product Specifications User Guide (UG475) [Ref 5], or the UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification User Guide (UG575) [Ref 11] for more information.
Syntax
Verilog and VHDL Syntax
Not applicable
XDC Syntax
set_property DCI_CASCADE {slave_banks} [get_iobanks master_bank]
Where
•slave_banks is a list of the bank numbers of the slave banks.
•master_bank is the bank number of the designated master bank.
XDC Syntax Example
# Designate Bank 14 as a master DCI Cascade bank and Banks 15 and 16 as its slaves
set_property DCI_CASCADE {15 16} [get_iobanks 14]
Affected Steps
•I/O planning
•Place Design
•DRC
•Write Bitstream
•report_power