MUXF_REMAP - 2022.1 English

Vivado Design Suite Properties Reference Guide

Document ID
UG912
Release Date
2022-06-08
Version
2022.1 English

MUXF_REMAP

The opt_design -muxf_remap option lets you convert MUXF7, MUXF8, and MUXF9 primitives to LUT3 to reduce routing congestion.

This property works similar to the LUT_REMAP property. If it is set to true on a MUXF* cell it will automatically trigger the MUX remap optimization during opt_design, and map those cells to a LUT3.

Unlike the LUT_REMAP property though, the MUXF_REMAP property also lets you limit the scope of the -muxf_remap optimization by setting the property to FALSE on individual MUXF cells. If it the property is set to FALSE on a MUXF cell, and the opt_design -muxf_remap command is called, it will prevent those MUXF cells from being mapped to a LUT3.

Refer to the Vivado Design Suite User Guide: Implementation (UG904) [Ref 20] for more information on optimization.

Architecture Support

All architectures.

Applicable Objects

MUXF Cells (get_cells)

Value

TRUE | 1 

°If opt_design -mux_remap is called, the presence of the MUXF_REMAP property with a value of TRUE has no additional effect.

°If opt_design -mux_remap is not called, the presence of the MUXF_REMAP property with a value of TRUE on specific cells will call MUX remapping for those specific cells only during opt_design.

FALSE | 0

°If opt_design -mux_remap is called, the presence of the MUXF_REMAP property with a value of FALSE will prevent the specified MUX from being remapped.

°If opt_design -mux_remap is not called, the presence of the MUXF_REMAP property with a value of FALSE has no additional effect.

Syntax

Verilog and VHDL Syntax

Not applicable

XDC Syntax

set_property MUXF_REMAP <value> <objects>

XDC Syntax Example

The following assigns the MUXF_REMAP property as FALSE to the specified MUXF primitives to exclude these cells from remapping when the opt_design -mux_remap command is used:

set_property MUXF_REMAP 0 [get_cells -hier \
-filter {name =~ cpu* && ref_name =~ MUXF*}]

Affected Steps

Logic Optimization (Opt Design)

See Also

CARRY_REMAP, page 166

LUT_REMAP, page 300