Description
An interface is a grouping of signals that share a common function, containing both individual signals and multiple buses. An AXI4-Lite master, for example, contains a large number of individual signals plus multiple buses, which are all required to make a connection. By grouping these signals and buses into an interface, the Vivado IP integrator can identify common interfaces and automatically make multiple connections in a single step.
An interface is defined using the IP-XACT standard. Standard interfaces provided by Xilinx can be found in the Vivado tools installation directory at data/ip/interfaces. See the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) [Ref 27] for more information on interface nets, pins, and ports.
A block design interface pin, or a bd_intf_pin object, is a point of logical connectivity on a block design cell. An interface pin allows the internals of a cell to be abstracted away and simplified for ease-of-use. Interface pins can appear on hierarchical block design cells, or leaf-level cells.
Related Objects
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X-Ref Target - Figure 2-5 
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A block design interface pin is attached to a block design cell (bd_cell), and can be connected to other interface pins (bd_intf_pin) or interface ports (bd_intf_port) by an interface net (bd_intf_net) in the block design, or diagram.
You can query the bd_intf_pins of bd_addr_space, bd_addr_seg, bd_cell, and bd_intf_net objects:
get_bd_intf_pins -of_objects [get_bd_cells clk_wiz_1]
You can also query the bd_addr_spaces, bd_addr_segs, bd_cells, and bd_intf_nets, of a specific bd_intf_pin:
get_bd_addr_spaces -of_objects [get_bd_intf_pins microblaze_0/*]
Properties
The specific properties on a block design interface pin object can vary depending on the type of the pin. The following table lists some of the properties assigned to a master AXI interface pin object, with example values:
Property Type Read-only Visible Value
BRIDGES string false false
CLASS string true true bd_intf_pin
CONFIG.ADDR_WIDTH string true true 32
CONFIG.ARUSER_WIDTH string true true 0
CONFIG.AWUSER_WIDTH string true true 0
CONFIG.BUSER_WIDTH string true true 0
CONFIG.CLK_DOMAIN string true true base_mb_clk_wiz_1_0_clk_out1
CONFIG.DATA_WIDTH string true true 32
CONFIG.FREQ_HZ string true true 100000000
CONFIG.HAS_BRESP string true true 1
CONFIG.HAS_BURST string true true 0
CONFIG.HAS_CACHE string true true 0
CONFIG.HAS_LOCK string true true 0
CONFIG.HAS_PROT string true true 1
CONFIG.HAS_QOS string true true 0
CONFIG.HAS_REGION string true true 0
CONFIG.HAS_RRESP string true true 1
CONFIG.HAS_WSTRB string true true 1
CONFIG.ID_WIDTH string true true 0
CONFIG.MAX_BURST_LENGTH string true true 1
CONFIG.NUM_READ_OUTSTANDING string true true 1
CONFIG.NUM_READ_THREADS string true true 1
CONFIG.NUM_WRITE_OUTSTANDING string true true 1
CONFIG.NUM_WRITE_THREADS string true true 1
CONFIG.PHASE string true true 0.0
CONFIG.PROTOCOL string true true AXI4LITE
CONFIG.READ_WRITE_MODE string true true READ_WRITE
CONFIG.RUSER_BITS_PER_BYTE string true true 0
CONFIG.RUSER_WIDTH string true true 0
CONFIG.SUPPORTS_NARROW_BURST string true true 0
CONFIG.WUSER_BITS_PER_BYTE string true true 0
CONFIG.WUSER_WIDTH string true true 0
LOCATION string false true
MODE string true true Master
NAME string false true M_AXI_DP
PATH string true true /microblaze_0/M_AXI_DP
TYPE string true true ip
VLNV string true true xilinx.com:interface:aximm_rtl:1.0
To report the properties for the bd_intf_pin object, you can copy and paste the following command into the Vivado Design Suite Tcl shell or Tcl Console:
report_property -all [lindex [get_bd_intf_pins */*] 0]
Or use the following Tcl script to report the properties of each bd_intf_pin object on each block design cell:
foreach x [get_bd_intf_pins -of_objects [get_bd_cells]] {
puts "Next Interface Pin starts here ..............................................."
report_property -all $x
}