The CONFIG_MODE property defines which device configuration mode or modes to use for pin allocations, DRC reporting, and bitstream generation.
IMPORTANT: COMPATIBLE_CONFIG_MODES property has been deprecated in the 2013.3 release, and is replaced by the CONFIG_MODE property.
Xilinx FPGAs can be configured by loading application-specific configuration data, or a bitstream, into internal memory through special configuration pins. There are two general configuration datapaths: a serial datapath used to minimize the device pins required, and parallel datapaths for higher performance configuration. The CONFIG_MODE property defines which modes are used for the current design.
Refer to the 7 Series FPGAs Configuration User Guide (UG470) [Ref 1], or the UltraScale Architecture Configuration User Guide (UG570) [Ref 7] for more information on device configuration modes.
Architecture Support
All architectures.
Applicable Objects
•Design (current_design)
Values
TIP: Not all of the following values apply to all device architectures. Refer to the 7 Series FPGAs Configuration User Guide (UG470) [Ref 1], or UltraScale Architecture Configuration User Guide (UG570) [Ref 7], for more information.
•S_SERIAL
•M_SERIAL
•S_SELECTMAP
•M_SELECTMAP
•B_SCAN
•S_SELECTMAP+READBACK
•M_SELECTMAP+READBACK
•B_SCAN+READBACK
•S_SELECTMAP32
•S_SELECTMAP32+READBACK
•S_SELECTMAP16
•S_SELECTMAP16+READBACK
•SPIx1
•SPIx2
•SPIx4
•SPIx8
•BPI8
•BPI16
Syntax
Verilog and VHDL Syntax
Not applicable
XDC Syntax
set_property CONFIG_MODE <value> [current_design]
Where <value> specifies the configuration mode.
XDC Syntax Example
# Specify using Configuration Mode Serial Peripheral Interface, 4-bit width
set_property CONFIG_MODE {SPIx4} [current_design]
Affected Steps
•I/O Planning
•Place Design
•report_drc
•Write Bitstream