DRIVE specifies output buffer drive strength in mA for output buffers configured with I/O standards that support programmable output drive strengths.
Architecture Support
All architectures.
Applicable Objects
•Ports (get_ports)
°Output or bidirectional ports connected to output buffers
Values
Integer values:
•2
•4
•6
•8
•12 (default)
•16
•24 (this value is not applicable to UltraScale architecture.)
Syntax
Verilog Syntax
For both inferred and instantiated output buffers, place the proper Verilog parameter syntax before the top-level output port declaration.
(* DRIVE = "{2|4|6|8|12|16|24}" *)
Verilog Syntax Example
// Sets the drive strength on the STATUS output port to 2 mA
(* DRIVE = "2" *) output STATUS,
VHDL Syntax
For both inferred and instantiated output buffers, place the proper VHDL attribute syntax before the top-level output port declaration.
Declare and specify the VHDL attribute as follows:
attribute DRIVE : integer;
attribute DRIVE of port_name : signal is value;
Where:
•port_name is a top-level output port.
VHDL Syntax Example
STATUS : out std_logic;
attribute DRIVE : integer;
-- Sets the drive strength on the STATUS output port to 2 mA
attribute DRIVE of STATUS : signal is 2;
XDC Syntax
set_property DRIVE value [get_ports port_name]
XDC Syntax Example
# Sets the drive strength of the port STATUS to 2 mA
set_property DRIVE 2 [get_ports STATUS]
Affected Steps
•I/O Planning
•Report Noise
•Report Power
See Also
Refer to the following design elements in the Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953) [Ref 25], or the UltraScale Architecture Libraries Guide (UG974) [Ref 26]:
•OBUF
•OBUFT
•IOBUF