TIMING-46: Multicycle Path with Tied CE Pins - 2024.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2024-06-05
Version
2024.1 English

One or more multicycle paths are defined between registers <cell_name1> and <cell_name2> with a direct connection and the CE pins connected to VCC (see constraint position <position> in the Timing Constraint window in the Vivado IDE). This might result in an inaccurate path requirement.