The Vivado Design Suite router prioritizes fixing hold over setup. This is because your design might work in the lab if you are failing setup by a small amount. There is always the option of lowering the clock frequency. If you have hold violations, the design most likely does not work.
In most cases, the router can meet the hold timing without affecting the setup. In
some cases (mostly due to errors in the design or the constraints), the setup time
is significantly affected. Improper hold checks are often caused by improper
set_multicycle_path constraints in which the
-hold was not specified. In other cases,
large hold requirements are due to excessive clock skew. In this case, AMD recommends that you review the clocking
architecture for that particular circuit. For more information, see this link
UltraFast Design Methodology Guide for FPGAs and SoCs
(UG949).
This can occur if your design meets setup timing post placement, but fails setup
post route. You can use the report_design_analysis command
with the -show_all option to view path delay due to routing
detours added by the router to fix hold violations. The following figure shows an example of
report_design_analysis report with the Hold Fix Detour column indicating the delay (in ps)
added to the timing path by the router due to hold fixing.
If you suspect that hold fixing is affecting timing closure, you can use one of the following to determine if this is the case: