Clock Phase Shift - 2024.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2024-06-05
Version
2024.1 English

A clock phase-shift corresponds to a delayed clock waveform with respect to a reference clock due to special hardware in the clock path. In AMD FPGAs, clock phase-shift is usually introduced by the MMCM or PLL primitives, when their output clock property CLKOUT*_PHASE is non-zero.