TIMING-31: Multicycle Path on Phase-Shifted Clock - 2024.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2024-06-05
Version
2024.1 English

The MMCM (or PLL) generated clock <clock_name> is phase shifted and is involved in one or several multicycle path constraints for setup only. Because the MMCM (or PLL) property PHASESHIFT_MODE is set to LATENCY, the legacy multicycle path constraint(s) might no longer be required.