Bus Skew Report Summary Section - 2024.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2024-06-05
Version
2024.1 English

The Bus Skew Report Summary section reports all the set_bus_skew constraints defined in the design. The following information is reported for each constraint:

Id
Constraint ID referred to later in the report. This information makes it easier to search for that constraint within the report.
From
Pattern provided for the set_bus_skew -from option.
To
Pattern provided for the set_bus_skew -to option.
Corner
Corner (Slow or Fast) in which the worst bus skew was computed.
Requirement
Bus skew target value.
Actual
Worst bus skew computed across all the paths covered by the constraint.
Slack
Difference between the worst bus skew and the constraint requirement.

In the following example, the design has only one bus skew constraint with a 1 ns requirement. The worst skew among all the paths covered by the constraint is 1.107 ns.



Note: A bus skew violation (WBSS) indicates that there is more skew between the different bits of an asynchronous bus than expected. This can result in incorrect data on the bus being captured in the destination clock domain. In such cases, the different bits of the bus could reflect a state sent by the source clock domain at different clock cycles. When one or more WBSS violations are left after routing, try a different routing or placement directive. For hardware stability, it is recommended to ensure that there is no bus skew violation left in the design.