Path from Input Port to Internal Sequential Cell - 2024.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2024-06-05
Version
2024.1 English

In a path from an input port to a sequential cell, the data:

  • Is launched outside the device by a clock on the board.
  • Reaches the device port after a delay called the input delay [Synopsys Design Constraints (SDC) definition].
  • Propagates through the device internal logic before reaching a sequential cell clocked by the destination clock.