Showing Connectivity - 2024.2 English - 2024.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2024-11-13
Version
2024.2 English

It can be useful to analyze a design based on connectivity. Run Show Connectivity to review the placement of all logic driven by an input, a block RAM, or a bank of DSPs. Show Connectivity takes a set of cells or nets as a seed, and selects objects of the other type.

Tip: Use this technique to build up and see cones of logic inside the design.

The following figure shows a block RAM driving logic inside the device including OBUFs. A synthesis pragma stops synthesis from placing the output flop in the block RAM during memory inferencing.

Figure 1. Show Connectivity