An intelligent design run (IDR) is a special type of implementation run that uses a complex flow to attempt to close timing. Because an IDR can be aggressive, a compile time of approximately 3.5 times that of a standard run can be expected.
The IDR presents a simple user interface around complex timing closure features, and achieves results at least on par with FPGA experts for a high percentage of designs.
Note: Intelligent Design Runs are not available for AMD Versal™
architectures. As an alternative, try the
Automatic QoR Suggestions flow to Automatically Generating and Applying Suggestions.