TIMING-40: Max Skew Violation between OSERDESE3 CLK and CLKDIV Pins Crossing SLRs - 2024.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2024-06-05
Version
2024.1 English

A max skew violation exists between the CLK and CLKDIV pins on the OSERDESE3 instance <NETLIST_ELEMENT>, and the clock networks are crossing SLRs to reach the clock pins. It is not recommended to drive the OSERDESE3 CLK and CLKDIV from clock sources placed in another SLR. Check your design.