Timing Path Details in Vivado IDE - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2023-10-19
Version
2023.2 English

The Timing Path Details in the Vivado IDE, as shown in the he following figure, shows the same information as is shown in the text report, seen in the previous figure.

Figure 1. Timing Path Details in Vivado IDE

The information on the path is displayed in five columns when the standard flow is used or six columns when the Incremental Compile is used:

  • Location

    Where the cell or port is placed on the device.

  • Delay Type

    The unisim primitive and the particular timing arc followed by the path. In case of a net, it shows the fanout (fo) and its status. A net can be:

    • Unplaced: The driver and the load are not placed.
    • Estimated: The driver or the load or both are placed. A partially routed net is also reported as estimated.
    • Routed: The driver and the load are both placed, plus the net is fully routed.
  • Incr(ns) (text report) / Delay (IDE report)

    The value of the incremental delay associated to a unisim primitive timing arc or a net. It can also show of a constraint such as input/output delay or clock uncertainty.

  • Path(ns) (text report) / Cumulative (IDE report)

    The accumulated delay after each segment of the path. On a given line, its value is the accumulated value from the previous + the incremental delay of the current line.

  • Netlist Resource(s) (text report) / Logical Resource (IDE report)

    The name of the netlist object traversed.

  • Pin Reuse (Incremental Compile only)

    Indicates whether the path is being reused from the reference run. Applicable values are ROUTING, PLACEMENT, MOVED, and NEW.

Each incremental delay is associated to one of the following edge senses:

  • r (rising)
  • f (falling)

The initial sense of the edge is determined by the launch or capture edge used for the analysis. It can be inverted by any cell along the path, depending on the nature of the timing arc. For example, a rising edge at the input of an inverter becomes a falling edge on the output.

The edge sense can be helpful in identifying that an overly-tight timing path requirement comes from a clock edge inversion along the source or destination clock tree.