Report Pulse Width - 2024.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2024-06-05
Version
2024.1 English

The Pulse Width Report (shown in the figure below) checks that the design meets min period, max period, high pulse time, and low pulse time requirements for each instance clock pin. It also checks that the maximum skew requirement is met between two clock pins of a same instance in the implemented design (for example, PCIe® clocks). The pulse width slack equations do not include jitter or clock uncertainty.

Equivalent Tcl command: report_pulse_width

When run from the Tcl Console, the pulse width report can be scoped to one or more hierarchical cells using the -cells option. When the report is scoped, only pins included inside the cell(s) are reported. This option is not available from the Report Pulse Width GUI.

Note: AMD Integrated Software Environment (ISE) Design Suite implementation calls this check Component Switching Limits.
Figure 1. Report Pulse Width