Interconnect Setting - 2024.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2024-06-05
Version
2024.1 English

Controls whether net delays are calculated based on the estimated route distance between leaf cell pins, by the actual routed net, or excludes net delay from timing analysis. This option is automatically set to Estimated for post-synthesis designs, and to Actual for post-implementation designs.

  • Estimated: For unplaced cells, the net delay value corresponds to the delay of the best possible placement, based on the nature of the driver and loads as well as the fanout. A net between unplaced leaf cell pins is labeled unplaced in the timing path report.

    For placed cells, the net delay depends on the distance between the driver and the load as well as the fanout. This net is labeled estimated in the timing path report.

  • Actual: For routed nets, the net delay corresponds to the actual hardware delay of the routed interconnect. This net is labeled routed in the timing path report.
  • None: Interconnect delays are not considered in the timing report and net delays are forced to zero.

Equivalent Tcl command: set_delay_model