RQS_TIMING-202: Add Extra Pipelining to Wide Multipliers - 2024.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2024-06-05
Version
2024.1 English

Wide multipliers (where at least one port is greater than the maximum width supported by the DSP slice in the given architecture) need extra pipelines to achieve the maximum operating frequency of the DSP slice. The number of pipeline stages require changes depending on the width required.

By adding extra stages to the output of wide multipliers in the RTL, synthesis moves them to optimal positions which makes recoding very simple.