TIMING-56: Missing Logically or Physically Excluded Clock Groups Constraint - 2024.2 English - 2024.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2024-11-13
Version
2024.2 English

Multiple clocks are user generated or auto-derived on the source pin(s) <pin_names> but are not logically or physically exclusive with respect to one another. To have the static timing analysis match the behavior in hardware, there cannot be multiple clocks generated on the same pin(s). In such cases, the clocks should be defined as physically or logically exclusive. The list of clocks generated on the source pin(s) is: <clock_names>.