Global Clock Resources Table - 2024.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2024-06-05
Version
2024.1 English

The Global Clock Resources table shows a summary for each clock net with important constraints and placement information, as shown in the following figure.

Figure 1. Report Clock Utilization – Global Clock Resources Table

The columns in the Global Clock Resources table are listed in the following table.

Table 1. Global Clock Resources Table Details
Column Description
Global Id Unique global clock net ID
Source Id ID of the clock generating primitive connected to the clock buffer
Driver Type/Pin Primitive pin connected to the clock net
Constraint

User physical constraint with highest precedence applied to the clock buffer. Priority rule is as follows:

  1. LOC
  2. CLOCK_REGION*
  3. PBLOCK

    * Does not apply to 7 series.

Site Clock buffer location set by the user or by the Vivado implementation tools.
Clock Region

Device clock region where the buffer is located.

Does not apply to 7 series.

Root

Clock region where the clock net CLOCK_ROOT is located.

Does not apply to 7 series.

Clock Delay Group

Name of the group of clock nets specified by the user to force routing matching by the AMD Vivado™ implementation tools.

Does not apply to 7 series.

Load Clock Region Number of clock regions where clock net loads are located.
Clock Loads Number of cells connected via clock pin loads.
Non-Clock Loads Number of non-clock pin loads, such as FDCE/CE pins for example.
Clock Period Period in ns of the timing clock which propagates on the clock net. If several clocks propagate on the same clock net, the smallest clock period is reported.
Clock Name of the timing clock which propagates on the clock net. If several clocks propagate on the same clock net, "Multiple" is reported.
Driver Pin Logical name of the clock net driver pin.
Net Logical name of the clock net segment connected to the clock driver pin.