AMD FPGA devices give you access to advanced clocking resources, including dedicated clock routing trees and clock modifying blocks (CMBs). Some CMBs can compensate for clock tree insertion delay using a phase-locked loop (PLL) circuit, which is present in PLL or MMCM primitives.
The amount of compensation depends on the insertion delay in the PLL feedback loop. In many cases, a PLL or MMCM drives several clock trees using the same type of buffer, including the feedback loop. Because the device can be large, the insertion delay across these clock tree branches doesn't always match the feedback loop delay.
You end up with over-compensated clocks when the feedback loop delay is greater than the source or destination clock delay. In this case, the sign of the CPR changes, and the tool removes skew optimism from the slack value. This adjustment ensures timing analysis doesn't introduce artificial skew at the common node clock paths.