The Challenging Timing Paths section highlights key properties of timing paths that failed the checks in the Assessment Details section. By default, the command evaluates 100 failing paths for each clock group. It analyzes the following factors:
- Net budget
- LUT budget
- Clock skew
The following figure shows an example of this analysis.
For these checks, the tool replaces estimated net or LUT delays with typical device-specific values, then recalculates the path budget. It also applies penalties to paths that start or end at block RAMs, DSPs, or other hard blocks. Additional penalties apply when the design cannot leverage clock tree skew to improve timing margin. The recalculated slack appears in the LUT Check Slack and Net Check Slack columns.
The SuggestionsID column shows any path-related QoR suggestions. If no suggestions are listed, investigate the paths and evaluate potential RTL modifications. If suggestions are present, applying them can resolve the issue without requiring code changes.
The Clock Skew section, shown in the figure labeled “Clock Skew Report,” displays the following information:
- Skew value
- Source and destination clock names
- Clock root for both clocks
- Clock uncertainty