Setup/Hold for Input Buses - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2023-10-19
Version
2023.2 English

Input buses are automatically inferred and their worst-case setup and hold requirements are displayed. Worst case data window for the entire bus is the sum of the largest setup and hold values. If the input ports are constrained, the slack is also reported.

An optimal tap point is reported for input clocks with IDELAY defined. The optimal tap point can be used to configure IDELAY for balanced setup and hold slack.

The source offset is the delta between two windows. The first window is defined by the setup and hold time of the input port with regard to the clock. The second window is derived from the input delay and the clock period. If the input clock is offset with this value, then it will be in the center of the window.

The following figure reports a design in which a DDR input bus, vsf_data[0:9], has a worst case data window of 1.663 ns. The ideal clock offset is 1.063 ns.

Figure 1. Setup and Hold Delays for Input Buses

Note: The optimal tap point can be specified by using the Tcl command:
set_property IDELAY_VALUE 13 [get_cells idelay_clk]