Phase Shift in Clock Reports - 2024.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2024-06-05
Version
2024.1 English

The clock phase shift information is provided in the Clock Report (report_clocks command). When a MMCM/PLL clock is phase-shifted and the MMCM/PLL has the PHASESHIFT_MODE property set to LATENCY, then the auto-derived clock is marked with the attribute S (pin phase-shifted with Latency mode). In addition, the clock details under the section Generated Clocks of the clock report show the amount of pin phase-shift that is accounted in the MMCM/PLL insertion delay.

Note: Only the delay corresponding to the auto-derived clock phase-shift is reported. The amount of phase-shift coming from the MMCM/PLL block is not included in the auto-derived clock waveform definition.

In the example below, the MMCM has the property PHASESHIFT_MODE set to LATENCY. The auto-derived clock clk_out1_clk_wiz_0 has no phase shift defined for the MMCM pin CLKOUT0 but the clock clk_out2_clk_wiz_0 has a -90 degrees phase shift defined for the MMCM pin CLKOUT2.

Attributes
  P: Propagated
  G: Generated
  A: Auto-derived
  R: Renamed
  V: Virtual
  I: Inverted
  S: Pin phase-shifted with Latency mode


Clock               Period(ns)  Waveform(ns)    Attributes  Sources
clk_in1             10.000      {0.000 5.000}   P           {clk_in1}
clk_out1_clk_wiz_0  10.000      {0.000 5.000}   P,G,A       {clknetwork/inst/mmcme3_adv_inst/CLKOUT0}
clk_out2_clk_wiz_0  10.000      {0.000 5.000}   P,G,A,S     {clknetwork/inst/mmcme3_adv_inst/CLKOUT2}


====================================================
Generated Clocks
====================================================

Generated Clock     : clk_out1_clk_wiz_0
Master Source       : clknetwork/inst/mmcme3_adv_inst/CLKIN1
Master Clock        : clk_in1
Multiply By         : 1
Generated Sources   : {clknetwork/inst/mmcme3_adv_inst/CLKOUT0}

Generated Clock     : clk_out2_clk_wiz_0
Master Source       : clknetwork/inst/mmcme3_adv_inst/CLKIN1
Master Clock        : clk_in1
Multiply By         : 1
Pin Phase Shift(ns) : -2.5  (-90 degrees)
Generated Sources   : {clknetwork/inst/mmcme3_adv_inst/CLKOUT2}