| Offset | R/W | Definition |
|---|---|---|
| 0x000 | RW |
LINK_ENABLE. Enable the receiver 1 – Enables the receiver core. Asserts the HPD signal when set. |
| 0x004 | RW |
AUX_CLOCK_DIVIDER. Contains the clock divider value for generating the internal 1 MHz clock from the AXI4-Lite host interface clock. The clock divider register provides integer division only and does not support fractional AXI4-Lite clock rates (for example, set to 75 for a 75 MHz AXI4-Lite clock). [27:24] – Valid values are 0-8. Non-zero value in this field will issue defers as per programmed value to DPCD read of LANE0_1_STATUS register. This functionality is needed to extend the clock recovery period from default. [[15:8] – This is the filter value, used to sample the AUX input with the AXI clock. It conveys the minimum number of clocks that AUX data is stable in terms of the AXI clock. But it does not represent an actual AUX pulse width. Allowed filter values are 0, 8, 16, 24, 32, 40, and 48. To calculate, use the largest filter value that satisfies the equation: filter value * AXI clock period ≤ 0.4 μs The allowed values are defined as: 0, 8 - AUX data should be constant for at least 7 clocks 16 − AUX data should be constant for at least 15 clocks 24 − AUX data should be constant for at least 23 clocks 32 − AUX data should be constant for at least 31 clocks 40 − AUX data should be constant for at least 40 clocks 48 − AUX data should be constant for at least 47 clocks Example: 50 MHz - Clock divider value: 50; the filter value should be 16 because the filter should be ≤ 20 (0.4 μs/(1/50 MHz)) and the nearest allowed value is 16. 100 MHz - Clock divider value: 100; the filter value should be 40 because the filter value should be ≤ 40 (0.4 μs/(1/100 MHz)) and the nearest allowed value is 40. 135 MHz – Clock divider value: 135; the filter value should be 48 because the filter value should be ≤ 54 (0.4 μs/(1/135 MHz)) and the nearest allowed value is 48 [7:0] Clock divider value. This value should satisfy the following conditions with 0.025 μs tolerance. (Clock divider value/8) * 3 * AXI clock period > 0.4 μs (as per RTL allowable value is 0.375 μs with tolerance) (Clock divider value/8) * 5 * AXI clock period < 0.6 μs (as per RTL allowable value is 0.625 μs with tolerance) (Clock divider value/2) * AXI clock period > 0.4 μs and < 0.6 μs |
| 0x008 | RW |
RX_LINE_RESET_DISABLE. RX line reset disable. This register bit can be used to disable the end of line reset to the internal video pipe for reduced blanking video support. [3] – End of line reset disable to the MST video stream4 [2] – End of line reset disable to the MST video stream3 [1] – End of line reset disable to the MST video stream2 [0] – End of line reset disable to the SST video stream/ MST video stream1 |
| 0x00C | RW |
DTG_ENABLE. Enables the display timing generator in the user interface. [0] – DTG_ENABLE: Set to 1 to enable the timing generator. The DTG should be disabled when the core detects the no-video pattern on the link. |
| 0x010 | RW |
USER_PIXEL_WIDTH. Configures the number of pixels output through the user data interface. The sink controller programs the pixel width to the active lane count (default). User can override this by writing a new value to this register. Use quad pixel mode in MST. [2:0] 1 = Single pixel wide interface. 2 = Dual pixel output mode. Valid for designs with 2 or 4 lanes. 4 = Quad pixel output mode. Valid for designs with 4 lanes only. |
| 0x014 | RW |
INTERRUPT_MASK. Masks the specified interrupt sources from asserting the axi_init signal. When set to a 1, the specified interrupt source is masked. This register resets to all 1s at power up. [31] – Mask for Cable disconnect/unplug interrupt [30] – CRC test start interrupt [29] – Mask MST Act sequence received interrupt [28] – Mask interrupt generated when DPCD registers 0x1C0, 0x1C1 and 0x1C2 are written for allocation/de-allocation/partial deletion [27] – Audio packet FIFO overflow interrupt [18] – Training pattern 3 start interrupt [17] – Training pattern 2 start interrupt [16] – Training pattern 1 start interrupt [15] – Bandwidth change interrupt [14] – TRAINING_DONE [13] – DOWN_REQUEST_BUFFER_READY [12] – DOWN_REPLY_BUFFER_READ [11] – VC Payload Deallocated [10] – VC Payload Allocated [9] – EXT_PKT_RXD: Set to 1 when extension packet is received [8] – INFO_PKT_RXD: Set to 1 when info packet is received [6] – VIDEO: Set to 1 when valid video frame is detected on main link. Video interrupt is set after a delay of eight video frames following a valid scrambler reset character [4] – TRAINING_LOST: Training has been lost on any one of the active lanes [3] – VERTICAL_BLANKING: Start of the vertical blanking interval [2] – NO_VIDEO: The no-video condition has been detected after active video received [1] – POWER_STATE: Power state change, DPCD register value 0x00600 [0] – VIDEO_MODE_CHANGE: Resolution change, as detected from the MSA fields. |
| 0x018 | RW |
MISC_CONTROL. Allows the host to instruct the receiver to pass the MSA values through unfiltered. [2] – When set to 1, I2C DEFERs will be sent as AUX DEFERs to the source device. [1] – When set to 1, the long I2C write data transfers are responded to using DEFER instead of Partial ACKs. [0] – USE_FILTERED_MSA: When set to 0, this bit disables the filter on the MSA values received by the core. When set to 1, two matching values must be detected for each field of the MSA values before the associated register is updated internally. |
| 0x01C | WO |
SOFTWARE_RESET_REGISTER. [8] – Soft reset control to external HDCP FIFOs. [7] – AUX Soft Reset. When set, AUX logic will be reset. [0] – Soft Video Reset: When set, video logic will be reset. Reads will return zeros. |