Non-Frame Buffer - 2.1 English

DisplayPort RX Subsystem LogiCORE IP Product Guide (PG233)

Document ID
PG233
Release Date
2023-05-25
Version
2.1 English

For non-frame buffer designs, the DisplayPort receiver core requires the generation of a video stream using the M and N values within the Main Stream Attributes to reconstruct an accurate stream clock. The DisplayPort Receiver core places this information on dedicated signals and provides an update flag to signal a change in these values. The following figure shows how to use the M and N values from the core to generate a clock. See section 2.2.3 of the DisplayPort Standard v1.2a for more details.

Figure 1. Receiver Clock Generation