Example Design - 2.1 English

DisplayPort RX Subsystem LogiCORE IP Product Guide (PG233)

Document ID
PG233
Release Date
2023-05-25
Version
2.1 English
Note: All example designs use the TED DP1.2 FMC Card from inrevium (TB-FMCH-DP3).

This chapter contains step-by-step instructions for generating an Application Example Design from the DisplayPort Subsystem by using the AMD Vivado™ Design Suite flow.

The following table shows the available example designs for the DisplayPort RX.

Table 1. Available Example Designs
GT Type Topology Video PHY Config Hardware GT Data Width BPC Processor
(TXPLL) (RXPLL)
GTXE2 Pass-through with HDCP1.3 CPLL CPLL KC705 + TED DP1.2 FMC 2-byte 10 MicroBlaze
Pass-through without HDCP1.3 CPLL CPLL KC705 + TED DP1.2 FMC 4-byte 10 MicroBlaze
GTHE3 Pass-through without HDCP1.3 QPLL CPLL KC105 + TED DP1.2 FMC 2-byte 10 MicroBlaze
GTHE4 RX only - CPLL ZCU102 + TED DP1.2 FMC 2-byte 10 A53
TX only QPLL - ZCU102 + TED DP1.2 FMC 2-byte 10 A53