| Offset | R/W | Definition |
|---|---|---|
| 0x0F8 | RO |
VERSION Register. For example, for displayport_v7.0, the VERSION REGISTER is 32’h07_00_0_0_00. [31:24] – Core major version [23:16] – Core minor version [15:12] – Core version revision [11:8] – Core Patch details [7:0] – Internal revision |
| 0x0FC | RO |
CORE_ID. Returns the unique identification code of the core and the current revision level. [31:24] – DisplayPort protocol major version [23:16] – DisplayPort protocol minor version [15:8] – DisplayPort protocol revision [7:0] – Core mode of operation 0x00: Transmit 0x01: Receive Depending on the protocol and core used, the CORE_ID values are as follows: DisplayPort Standard v1.1a, Receive core: 32’h01_01_0a_01 DisplayPort Standard v1.2a, Receive core: 32’h01_02_0a_01 |
| 0x110 | RO |
USER_FIFO_OVERFLOW. This status bit indicates an overflow of the user data FIFO of pixel data. This event might occur if the input pixel clock is not fast enough to support the current DisplayPort link width and link speed. [11] – Video Timing FIFO_OVERFLOW_FLAG (Stream 4): 1 indicates that the Video Timing FIFO has overflowed for stream4. [10] – Video Timing FIFO_OVERFLOW_FLAG (Stream 3): 1 indicates that the Video Timing FIFO has overflowed for stream3. [9] – Video Timing FIFO_OVERFLOW_FLAG (Stream 2): 1 indicates that the Video Timing FIFO has overflowed for stream2. [8] – Video Timing FIFO_OVERFLOW_FLAG (Stream 1): 1 indicates that the Video Timing FIFO has overflowed. [7] – Video Unpack FIFO_OVERFLOW_FLAG (Stream 4): 1 indicates that the Video unpack FIFO is overflowed for stream4. [6] – Video Unpack FIFO_OVERFLOW_FLAG (Stream 3): 1 indicates that the Video unpack FIFO has overflowed for stream3. [5] – Video Unpack FIFO_OVERFLOW_FLAG (Stream 2): 1 indicates that the Video unpack FIFO has overflowed for stream2. [4] – Video Unpack FIFO_OVERFLOW_FLAG (Stream 1): 1 indicates that the Video unpack FIFO has overflowed. [3] – FIFO_OVERFLOW_FLAG (Stream 4): 1 indicates that the internal FIFO has detected an overflow condition for Stream 4. This bit clears upon read. [2] – FIFO_OVERFLOW_FLAG (Stream 3): 1 indicates that the internal FIFO has detected an overflow condition for Stream 3. This bit clears upon read. [1] – FIFO_OVERFLOW_FLAG (Stream 2): 1 indicates that the internal FIFO has detected an overflow condition for Stream 2. This bit clears upon read. [0] – FIFO_OVERFLOW_FLAG (Stream 1): 1 indicates that the internal FIFO has detected an overflow condition for Stream 1. This bit clears upon read. |
| 0x114 | RO |
USER_VSYNC_STATE. Provides a mechanism for the host processor to monitor the state of the video datapath. This bit is set when vsync is asserted. [3] – State of the vertical sync pulse for Stream 4. [2] – State of the vertical sync pulse for Stream 3. [1] – State of the vertical sync pulse for Stream 2. [0] – State of the vertical sync pulse for Stream 1. |